The present invention concerns an electrically addressable, non-volatile read-only memory, comprising an electrically addressable non-volatile read-only memory, comprising a plurality of memory cells which in a write operation comprising a part of the manufacturing process of the read-only memory, permanently each are assigned one or two or more logic states according to a determined protocol which in the memory defines permanently written or stored data, and a passive matrix of electrical conductors for the addressing. The passive electrical conductor matrix comprises a first and a second electrode structure in respective mutually spaced apart and parallel planes and with parallel electrodes in each plane and provided such that the electrodes form a substantially orthogonal x,y matrix wherein the electrodes in the first electrode structure comprise the columns of the matrix or x electrodes and the electrodes in the second electrode structure comprise the rows of the matrix or y electrodes, wherein at least a portion of the volume between the intersection of an x electrode and a y electrode defines a memory cell in the read-only memory. The mutually overlapping portions of the x electrode and the y electrode in the memory cell, each defines a contact area in the memory cell, wherein at least one semiconductor material is provided between the electrode structures and with rectifying properties in relation to a selected electrical conducting electrode material, and an electrical isolating material, wherein the semiconductor material in electrical contact with an electrode in the memory cell forms a diode junction in the interface between semiconductor material and electrode material.
The invention also concerns a read-only memory device which comprises one or more read-only memories according to the invention, and a read-only memory device which comprises two or more read-only memories according to the invention.
Matrix addressing of data storage locations or bit spots on a plane is a simple and efficient way of achieving a great number of accessible memory locations with a moderate number of electrical addressing lines. In a square x,y matrix with n lines respectively both in the x direction and the y direction the number of memory locations scales as n2. In one form or another this basic principle is at present implemented in a large number of different embodiments of solid state memory means. In these the memory location comprises a simple electronic circuits which communicates to the outside via the intersection in the matrix and a memory element, typically a charge storage device. Even if such means have been technically and commercially very successful, they have a number of disadvantages, and particularly each memory location has a complex architecture which leads to increased costs and reduced data storage density. In the large subclass of so-called volatile memory means the circuits must constantly sustain a current supply with accompanying heating and consumption of electric power in order to maintain the stored information. On the other hand non-volatile means avoid this problem, but with the trade-off of a reduced access and switching time as well as increased consumption and high complexity.
Prior art provides a number of examples of semiconductor-based read-only memories with electrical addressing in passive matrix. Thus U.S. Pat. No. 4,099,260 (Lynes and al.) discloses a semiconductor-based read-only memory (ROM) made as a large scale integrated device wherein self-isolating bit line surface areas of one conduction type are formed in a semiconductor substrate and directly in a bulk area in the opposite conduction type. Channel stop areas of the same conduction type as the bulk area are formed in the intervals between the bit line areas. Metallic word lines which lie above and are orthogonal to the bit line areas, are formed separately from these by means of an isolating layer. The memory cell comprises a single Schottky diode. A diode of this kind will be formed or not at each intersection between a word line and a bit line depending on whether or not an opening is formed in the isolating layer during manufacturing in order to permit the word line to contact a lightly doped portion of the bit line. A ROM of this kind is stated to have a small area, high speed, low power dissipation and low cost.
Further there are from U.S. Pat. No. 4,000,713 (Bauge and Mollier) known a device with semiconductor elements, such as Schottky diodes and transistors integrated in the form of a matrix on chips. The matrix may be custom designed in order to provide a desired function. For instance it may be used as AND or OR matrices in programmable logic arrays (PLA) or as read-only memories which are stated to have better properties with regard to storage density and power dissipation. A first electrode structure with parallel metal electrodes of somewhat different design is provided on a semiconductor substrate of for instance the p type. An oxide layer is provided on a semiconductor substrate and openings are formed in the oxide layer to provide anode contacts and cathode contacts via metallic lines which constitute a first metal level in the electrode matrix. Two n+ areas are located under the cathode contacts. These areas extend to underlying collector layers such that a Schottky diode is formed. Above the first metal level or electrode level an isolating layer is provided and over this a second metal level which comprises for instance an orthogonal second electrode structure. Openings through the isolating layer ensure contact with a cathode contact in a group of such which are included in the separate element in the matrix.
Finally there are from U.S. Pat. No. 5,272,370 (French) known a thin-film ROM device based on a matrix of open and closed memory cells formed in a stack of thin films on glass or another substrate. Each closed memory cell comprises a thin-film diode and it may by using stacks of semiconductor films, for instance of hydrogenated amorphous silicon, wherein the separate films are of different conduction types, be obtained diodes with different conduction characteristics. Thereby the information content in the ROM matrix may be increased. Each memory element which is formed with diode structure, may then be set with different logic levels according to some manufacturing protocol. Where the memory element does not have a diode structure or where the semiconductors are covered by an isolating layer such that no electrode contact is formed, the memory element may be used to form a determined first logic level, for instance logical 0.
Even though the above-mentioned prior-art devices all realize electrical addressing in passive matrix in an as per se known manner by providing diode junctions in closed electrode contacts, they have partly due to using different types of semiconductors a relatively high degree of complexity. In the ROM device as disclosed in the last-mentioned publication (U.S. Pat. No. 5,272,370) it may, however, be possible to store more than two logical values in the matrix, but this presupposes use of different diode types and hence several layers of differently doped semiconductors in the bit spot with diode junction.
The object of the present invention is hence primarily to provide a read-only memory or ROM which permits electrical addressing in passive matrix to the separate memory cell in the read-only memory and which does not need refreshment in order to keep the data stored in the memory cell, while the read-only memory shall be simply and cheaply realized using as per se known technologies and methods as applied in the semiconductor and thin-film technology.
Particularly it is the object of the present invention to provide a non-volatile read-only memory based on the use of organic materials, for instance polymer materials, which realized in thin-film technology may be used both in conductors, isolators and semiconductor materials, something which supposedly shall provide more flexible technical solutions and especially a much reduced cost than would be the case when using crystalline inorganic semiconductors.
Further it is also an object to provide a read-only memory which allows a multilevel coding of predetermined memory cells or memory locations.
Finally it is the object of the present invention to provide a read-only memory which may be used to realize a volumetric read-only memory device.
These and other objects and advantages are achieved according to the invention with a read-only memory which is characterized in that a first logic state of a memory cell in the read-only memory is formed by an active portion of the semiconductor material covering the whole contact area in the memory cell, the diode junction comprising the whole contact area of the memory cell, that a second logic state in a selected memory cell in the read-only memory is formed by at least one electrode structure in the memory cell being covered by the isolating material, that one or several additional logic states in a memory cell in the read-only memory is formed by an active portion of the semiconductor material covering only a part of the contact area and/or that the diode junction only comprises a part of the contact area, such that the data which are stored in the memory may be represented by the logic states in a binary or multi-valued code, and that a logic state in each case is given by the impedance value of the memory cell, said impedance value substantially being given by one of the following factors: the impedance characteristics of the semiconductor material, the impedance characteristics of the isolating material, the extension of the active portion of the semiconductor material, the extension of the part of the contact area which forms the diode junction, and the impedance characteristic of the diode junction.
A first read-only memory device according to the invention is characterized in that the read-only memory is provided on a substrate of semiconductor material or between substrates of semiconductor material and via the substrates connected with driver and control circuits for driving and addressing, said driving and control circuits being integrated in the substrate or the substrates and realized in a semiconductor technology compatible with the substrate material; and a second read-only memory device according to the invention is characterized in that the read-only memory is stacked in horizontal layers in order to provide a volumetric memory device, that the volumetric memory device is provided on a substrate of semiconductor material or between substrates of semiconductor material and via the substrate or the substrates connected with driver and control circuits for driving and addressing, said driving and control circuits being integrated with the substrate or the substrates and realized in a semiconductor technology compatible with the substrate material.
Wherein the read-only memory according to the invention constitutes a binary logic memory with only one additional logic state, it is advantageous that the first logic state which either represents a logical 0 or a logical 1, is given by the effective forward bias resistance of a diode formed in a memory cell wherein the semiconductor material contacts both the x electrode and the y electrode, and that additional logic state which correspondingly represents either a logical 1 or a logical 0 is given by a selected resistance value for the isolating material provided in a memory cell wherein the semiconducting material at most contacts either the x electrode or the y electrode, said isolating material in a memory cell preferably having an infinite resistance value.
Wherein the read-only memory according to the invention is realized as a multilevel logic memory with two or more further logic states, it is advantageous that the first logic state is given by the effective forward bias resistance of a diode formed in a memory cell wherein the semiconductor material contacts both the x and y electrodes and that the additional logic states are given by determined resistance values for the isolating material provided in a memory cell wherein the semiconductor material at most contacts either the x electrode or the y electrode and the selected determined resistance value in each case lies between the effective forward bias resistance of a memory cell formed in the diode, and infinite.
In a first embodiment of the read-only memory according to the invention the isolating material in selected memory cells is provided between the electrode structures in the form of a separate layer-like isolator patch which wholly or partly covers at least one of the electrodes in the memory cell, a selected memory cell dependent on the active portion of the semiconductor material and/or the diode junction part of the contact area in the latter case acquiring a logic state which corresponds to a level of a multi-valued code.
If the isolator patch in said first embodiment wholly or partly covers only one of the electrodes, the semiconductor material may be provided between the electrode structures in a global layer and besides over the isolator patch in the selected memory cells. If the isolator patch wholly or partly covers both electrodes, the semiconductor material may preferably be provided between the electrode structures and adjacent to the isolator patches in the selected memory cells, such that semiconductor material and the isolator patches mutually flush in a common continuous layer.
In a second embodiment of the read-only memory according to the invention the isolating layer is provided between the electrode structures in the form of a substantially global layer which covers at least one of the electrode structures and with removed portions in selected memory cells, such that removed portion wholly or partly exposes the electrodes in a selected memory cell, said memory cell dependent on the active portion of the semiconductor material and/or the diode junction part of the contact area in the latter case acquiring a logic state which corresponds to a level in a multi-valued code.
If the isolating layer in said second embodiment covers only one of the electrode structures, the semiconductor material may preferably be provided between the electrode structures and over the isolating layer in a global layer and besides contact the electrode structures in the removed portions of the isolation layer. If the isolating layer covers both the electrode structures, the semiconductor material may preferably be provided only between the electrode structures and adjacent to the isolation layer in the selected memory cells, such that the semiconductor material and the isolating layer mutually flush in a common continuous layer. Finally, it is according to the invention advantageous that the semiconductor material is amorphous silicon, polycrystalline silicon or an organic semiconductor, said organic semiconductor preferably being a conjugated polymer.
According to the invention the semiconductor material may be an anisotropic conductor. Preferably the semiconductor material may comprise more than one semiconductor or possibly also be added or combined with an electrical conducting material.
Preferably the semiconductor material, the isolating material and the electrode structures are realized as thin films.
The background of the invention and various examples of its embodiment shall now be discussed in more detail in the following with the reference to the accompanying drawing.